By Nuno Lourenço, Ricardo Martins, Nuno Horta
This ebook introduces readers to quite a few instruments for computerized analog built-in circuit (IC) sizing and optimization. The authors supply a old standpoint at the early equipment proposed to take on automated analog circuit sizing, with emphasis at the methodologies to dimension and optimize the circuit, and at the methodologies to estimate the circuit’s functionality. The dialogue additionally contains strong circuit layout and optimization and the newest advances in layout-aware analog sizing techniques. The authors describe a strategy for an automated circulate for analog IC layout, together with info of the inputs and interfaces, multi-objective optimization thoughts, and the improvements made within the base implementation by utilizing computing device leaning concepts. The Gradient version is mentioned intimately, besides the the way to comprise format results within the circuit sizing. The options and algorithms of all of the modules are completely defined, allowing readers to breed the methodologies, increase the standard in their designs, or use them as place to begin for a brand new instrument. an intensive set of software examples is integrated to illustrate the features and contours of the methodologies described.
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Extra info for Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
81] Berkol et al.  AIDA [87–89] Simulator (Spectre®, Eldo® or HSPICE®) Circuit simulator Bias driven equations Circuit simulator Circuit simulator BSIM4 equations Symbolic models MOO Design plan to iteratively solve model equations Nonlinear deterministic optimizer MOO Symbolic models Optimization-based Youssef et al.  Fitted functions Optimization-based Vancorenland et al.  Ranjan et al. 1 Overview of layout-aware sizing tools Multiple B*-trees Enum. of all floorplans Coded slicing-tree Template based/assisted placement Layout description Layout generator Placer Automatic electromigration-aware WT and global routing in-loop script Channel router Template-based Cadence chip assembly router® Router Yes Yes Yes Yes Yes Yes No No Eq.
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Historically, both SA and GA have been used intensively, in this sense is natural to consider both evolutionary and annealing approaches. Given the recent experiments with swarm intelligence in this domain, and to broad the scope of the implemented framework, this class of methods were also considered. From a brief perusal of the multi-objectives implementations, the ideas like non-sorted domination or crowding distance (further described in Chap. 4 of this book) presented in NSGA-II are reused by several other methods.
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects by Nuno Lourenço, Ricardo Martins, Nuno Horta